The present invention relates to a paging receiver, and more particularly a circuit for receiving a message signal by stabilizing the bias of the paging receiver when periodically controlling a voltage source.
Generally, the paging receiver receives a radio frequency signal (hereinafter referred to as RF signal) transmitted by a paging system, converts the RF signal into an intermediate frequency signal that is demodulated into the original digital data. The demodulated signal is an analog signal shaped into a digital waveform based on a reference signal and applied to a controller. The controller identifies the digital data as self-data, then generates a calling sound signal through the speaker.
Such paging receiver makes use of a small DC battery, and thus power consumption should be minimized so as to lengthen the life span of the battery. To this end, the power supplying of the RF components is controlled so as to reduce the power consumption of the battery. The RF components include a RF receiver, a demodulator and a waveform shaping circuit which are the main cause of most power consumption.
The RF signal transmitted by the paging system is of a given data form. Assuming the RF signal is in the form of POCSAG codes, the signal comprises a preamble part, word sync and frame data. The controller periodically supplies the power to the RF components in order to search for the preamble part (Preamble Search Mode). If the preamble part is detected, the controller keeps on supplying the power and searches for the word sync. Once the word sync is detected, the controller stops supplying the power, thereafter resupplying the power in the self-frame period (Address Search Mode).
However, in such a conventional paging receiver, since all the RF components should be supplied with the power in the preamble search mode, there occurs a large power consumption. The reason is that the power should be supplied to the RF components before receiving the substantial message data, so as to establish a reference signal voltage.
In view of the fact above, there is disclosed an apparatus for saving the power by sequentially supplying the power to the RF components in the U.S. Pat. No. 4,479,261 issued to Japanese Nippon Electric Co., Ltd. on Oct. 23, 1984, as shown in FIGS. 1-3 attached to the present application. In this case, a voltage source control signal with J period through the first and second timers 34 and 35 is provided by the controller 13. The first and second switch circuits 16 and 17 are sequentially switched on in response to the voltage source control signal so as to supply the power of the battery 15 to the waveform reshaping circuit 12 and the receiver 11.
Specifically, if the first timer 34 generates a voltage source control signal as shown in FIG. 3B at a time point D1, the first switch circuit 16 switches on to apply the power to the waveform reshaping circuit 12. Then the output voltage of the low pass filter 21 of the waveform reshaping circuit 12 as showing in FIG. 2 is supplied as the reference signal to the capacitor 24 connected in parallel to the reference terminal (-) of the voltage comparator 25. Thereafter, if the second timer 35 generates a voltage source control signal as shown in FIG. 3C with a J period at a time point D2, the second switch circuit 17 switches on to supply the power to the receiver 11 for enabling conversion and demodulating the RF signal received through the antenna 10. Thus the power supplying of the waveform reshaping circuit 12 and the receiver 11 are controlled by the J period, thereby reducing the power consumption of the receiver 11.
In such controlling of the power, the reference voltage charged in the capacitor 24 at a time point D2 when the receiver 11 is in a reception mode does not effectively serve to determine the logical state of the data output from the receiver 11. The reason is that if the receiver 11 receives the RF signal after the time point D2, the level of the reference voltage is increased by the resistor 23 and the capacitor 24 according to the logical state of the received data. And at the time point D3, the reference voltage is changed to the average voltage of the substantial data.
Thus the charged voltage of the capacitor 24 that serves as the reference signal is delayed by J and K periods after generation of the voltage source control signal, thereby stabilizing the bias voltage. Therefore the data received in the K period suffers a duty change by the unstable reference voltage, so that there may occur data receiving error. In order to prevent such error the reference voltage must be stabilized by sequentially driving the first and second switch circuits 16 and 17 prior to the reception of data. Such stabilizing apparatus is disclosed in the U.S. Pat. No. 4,631,737 issued to the Motorola Company of the U.S.A. on Dec. 23, 1986.
This bias stabilizing apparatus is briefly described with reference to FIGS. 4-7. The RF signal received through the antenna 40 is converted and demodulated in the receiver 41. The demodulated signal output from the receiver 41 has a voltage corresponding to its logical state, and is applied to a comparing terminal of a limiter 44. The demodulated signal is also applied to a peak detector 45 and a valley detector 47. The peak detector holds the peak value of the received data as shown in FIG. 7B, while the valley detector 47 holds the valley value of the received data as shown in FIG. 7C. The peak and valley values are averaged and then applied to the limiter as a reference voltage. Thus, the limiter 44 receives as the reference signal the voltage averaged according to the logical state of the received data, and therefore determines the logical state of the demodulated signal input through the comparing terminal, and then applies the output to the controller.
FIGS. 5 and 6 are respectively the circuits of the peak and valley detectors. When detecting the peak and valley values, there occurs a delayed time caused by each component. As shown in FIG. 7, d1-d3 period is a delayed time period which is representative of a charging time of the capacitor 56. Only by charging the capacitor 56 are operated the transistors 54 and 76 that are respectively of static current sources of the peak and valley detectors 45 and 47. After the time point d3, there is needed the period d3-d4 in order to charge the capacitor 60 with the peak value and to discharge it to the valley value. Consequently it is the time point d4 when the limiter 44 works to determine the data with the substantially stabilized bias.
Such bias stabilizing apparatus, using the average of the peak and valley values of the received data, needs all the RF components (RF receiver, demodulator, waveform reshaping circuit) being provided with the voltage source, thus increasing the power consumption.